ASIC Design Engineer - Pixel IP ANE
Core
Designing high-speed, high-performance subsystems for the next-generation Apple Neural Engine (Pixel IP ANE) to enable AI/ML capabilities in consumer products.
Role type
Senior ASIC Design Engineer (Pixel IP ANE)
Builds
Next-generation Apple Neural Engine hardware for AI/ML workloads
Domain
Semiconductor / Hardware / AI/ML Infrastructure
Deliverable
production ML models
Required skills
RTL design, Computer architecture, AMBA protocols, Design verification, Formal verification, Physical design, Static timing analysis, Clock domain crossing analysis, DFT/BIST integration
Preferred skills
Large high-speed compute system design, Synthesis, Power intent management
Technologies
AMBA, RTL, Synthesis tools, Static Timing Analysis tools, DFT/BIST frameworks
Responsibilities
Design high-speed, high-performance subsystems; Collaborate with verification teams for full design validation; Work with physical design teams to produce high-quality netlists; Analyze clock domain crossing designs for correctness; Partner with DFT and BIST teams to ensure full testability.
Seniority
Senior, hands-on IC
