Design Verification Engineer
Core
Design Verification of Analog and Mixed Signal ASIC IPs to ensure bug-free first silicon for System on a Chip (SoC)/IP.
Role type
Senior IC Design Verification Engineer
Builds
Pre-silicon verification environments and test-benches for camera interfaces, USB3 controllers, and SoC components.
Domain
Semiconductor / Hardware Design
Required skills
Verilog, System Verilog, Python, UVM, constrained randomization, functional/code coverage, assertion methodology, simulation and debugging tools (VCS, Verdi, Indago), computer architecture knowledge
Preferred skills
N/A
Technologies
VCS, Verdi, Indago, Python, Perl, UVM
Responsibilities
Develop detailed test and coverage plans based on micro-architecture; create verification environments including stimulus, checkers, assertions, trackers, and coverage; execute verification plans including design bring-up, regression, and debug of test failures; develop block, IP, and SoC level test-benches; track and report DV progress using metrics like bugs and coverage.
Seniority
Senior, hands-on IC