Design Verification
Core
Design and architect specifications for SoC, IP, and subsystems while developing verification methodologies and test benches.
Role type
Senior IC design verification engineer
Builds
SoC, IP, and subsystems including Neural Engine, DRAM, memory controllers, codecs, high-speed IO, and power management
Domain
Semiconductor hardware design and verification
Required skills
SystemVerilog, UVM methodology, VCS/xcelium/modelSim simulation, formal verification (JasperGold), coverage analysis (Mentor InFact/Cadence), C/C++ modeling, computer architecture knowledge, waveform debugging (Indago/Verdi), scripting (Perl/tcl/Python), version control (Perforce/Git/Clearcase)
Preferred skills
N/A
Technologies
SystemVerilog, UVM, VCS, xcelium, modelSim, JasperGold, Mentor InFact, Cadence vManager/IMC, Indago, Verdi, Perforce, Git, Clearcase
Responsibilities
Develop test plans, tests, and coverage plans; collaborate with design and architecture teams to define use cases and corner conditions; ensure quality of SoC, IP, and subsystems; debug functional and performance issues using waveform tools.
Seniority
Senior, hands-on IC
