Design Verification Engineer
Core
Verifying complex digital IPs by building verification plans and test benches to ensure functional, performance, and error condition coverage for chip blocks.
Role type
Senior IC design verification engineer (digital IP)
Builds
Block-level verification environments and test cases for digital chips
Domain
Semiconductor / Digital Hardware Design
Required skills
System Verilog, UVM, constrained random testing, System Verilog Assertions, formal verification, C programming, Python/Perl automation, Finite State Machine design, CAD simulation debugging
Responsibilities
Create block-level verification plans and test benches using formal verification and UVM; Develop drivers, tests, reference models, and checkers using System Verilog and UVM; Debug test failures and collaborate with designers to fix issues; Participate in code reviews to propose efficiency improvements; Architect block-level verification elements and assist in system-level verification environments; Use functional and code coverage to track progress and gauge tape-out readiness.
