Design Verification
Core
Design verification engineer responsible for low power verification of Apple System on Chips (SOCs), focusing on power state transitions and power manager integration.
Role type
Senior IC hardware verification engineer (low power/SOC)
Builds
System on Chip (SOC) designs with verified low power functionality and power management integration
Domain
Semiconductor / Hardware Design / Low Power Verification
Required skills
System Verilog, C programming, Perl/Python scripting, UPF (power intent), AXI/AMBA protocols, low power design fundamentals, digital logic design, ARM/X86 architecture
Technologies
System Verilog, C, Perl, Python, UPF, AXI, AMBA, CAD simulation tools
Responsibilities
Develop test plans and coverage plans for low power functionality; Create directed and random tests for power manager integration; Write C-based test cases and System Verilog behavioral models; Automate verification tasks using Perl/Python scripts; Run chip-level simulations and debug failing test cases; File and track bug reports for simulation failures
Seniority
Mid-level, hands-on IC
