Design Verification
Core
Develop verification strategies and scalable SystemVerilog UVM test-benches to support Apple's Display Technologies portfolio for next-generation products.
Role type
Senior IC design verification engineer (SoC)
Builds
Production SoC chips and sub-systems for Apple Display Technologies
Domain
Semiconductor / Digital IC Design
Required skills
SystemVerilog UVM, constrained random test generation, SystemVerilog Assertions (SVA), Python scripting, C/C++ for reference models, RTL design concepts, waveform analysis, regression automation
Preferred skills
N/A
Technologies
SystemVerilog, UVM, Python, C, C++, Perl, Tcl, Verdi/SimVision, Indigo
Responsibilities
Develop verification strategies, test plans, and coverage requirements; Design and maintain scalable SystemVerilog UVM test-benches; Write and maintain test cases using directed/constrained random generation and assertions; Run RTL and gate-level simulations and analyze failures; Build and maintain automated regression flows; Coordinate with architects for end-to-end validation.
Seniority
Senior, hands-on IC
