Digital/Mixed Signal Modeling/Verification Engineer
Core
Design Verification Engineer responsible for verifying functionality and performance of Apple's premier System on Chips (SoCs), specifically owning RNM/SystemVerilog behavioral modeling and verification of analog/RF blocks.
Role type
Senior IC mixed-signal verification engineer
Builds
Apple's premier System on Chips (SoCs)
Domain
Semiconductor hardware, analog/RF circuit design
Required skills
RNM coding in SystemVerilog, analog/RF circuit theory/topologies, self-checking model development, assertion development for analog/digital specs, AMS simulation environment setup, complex digital-on-top testbench debugging
Preferred skills
Cadence mixed signal verification environment, reading analog schematics, modeling mixed signal/RF blocks (biasing networks, power regulators, bandgaps, Opamp's, OTA's, data converters, LNA, PA, mixers), high frequency PLL modeling