Design Verification Engineer II
Core
Develop and execute verification plans for Wireless MCU SoCs, including mixed-signal designs, to ensure functionality before silicon production.
Role type
Senior IC design verification engineer
Builds
Wireless MCU System-on-Chips (SoCs) with embedded CPUs, analog/digital peripherals, security, and power management
Domain
Semiconductor / IoT / Wireless Connectivity
Required skills
SystemVerilog, UVM, constrained-random testing, functional coverage, assertions (SVA), RTL debugging, Python/Perl/TCL scripting, CDC/RDC verification, mixed-signal verification
Preferred skills
RISC-V core verification, AI/ML component verification, low-power verification concepts, SoC architecture knowledge
Technologies
SystemVerilog, UVM, OVM, Python, Perl, TCL, AMBA, AXI, APB
Responsibilities
Develop and execute verification plans for SoC/IP blocks; Build and maintain SystemVerilog/UVM-based testbenches; Create directed and constrained-random test cases; Drive functional coverage closure and regression analysis; Debug RTL and verification failures across simulation/emulation environments; Mentor junior engineers and contribute to verification strategy
Seniority
Senior, hands-on IC
