Senior Principal Physical Design Engineer
Core
Senior Principal Physical Design Engineer responsible for full-chip ownership from architecture to GDSII, driving complex SoC designs to production for server, storage, and networking applications.
Role type
Senior Principal Physical Design Engineer (Backend)
Builds
Custom connectivity solutions and SoC/silicon products for hyperscalers and data center infrastructure
Domain
Semiconductor / Physical Design / AI Infrastructure
Required skills
Synthesis, Place and Route, CTS, STA, Physical Verification, Formal Verification, System Verilog/Verilog, DFT, IP Integration, Python/Perl Scripting, Cadence/Synopsys Tools
Preferred skills
DFT test coverage and debug, ECO methodologies, Stuck-at and transition scan test insertion
Technologies
Cadence, Synopsys, 16nm/7nm nodes, CXL, PCIe, Ethernet, NVLink, UALink
Responsibilities
Perform synthesis, timing closure, and formal verification at block and full-chip levels; drive multiple complex designs from architecture to GDSII; collaborate with IP vendors for RTL and hard-mac blocks; utilize backend tools for technologies 16nm or less (preferably 7nm or less).
Seniority
Senior, hands-on IC
