Senior Design Verification Engineer
Core
Define and deliver robust verification for next-generation connectivity silicon enabling rack-scale AI infrastructure.
Role type
Senior IC design verification engineer (connectivity protocols)
Builds
PCIe Gen 6/Gen 7, UALink, and UCI connectivity products for AI accelerators and data centers
Domain
Semiconductor hardware design, high-speed connectivity protocols, AI infrastructure
Required skills
SystemVerilog, UVM, testbench development, coverage closure, simulation debugging, assertion writing, regression automation
Preferred skills
PCIe/UALink protocol verification, formal verification, emulation, Python/Perl/Tcl scripting, AI system architecture knowledge
Technologies
SystemVerilog, UVM, PCIe Gen 6/7, UALink, UCI, Python, Perl, Tcl
Responsibilities
Develop block- and subsystem-level verification plans; Build reusable UVM-based testbenches and agents; Drive functional and code coverage analysis; Debug simulation failures using waveform analysis; Partner with design teams on issue isolation and silicon bring-up readiness
Seniority
Senior, hands-on IC
