Tech Lead, Digital Design Engineer
Core
Lead front-end digital design for high-performance switch ASICs enabling rack-scale AI infrastructure.
Role type
Senior IC digital design engineer (switch ASIC)
Builds
High-performance networking and server connectivity ASICs
Domain
Semiconductor hardware design, AI infrastructure, high-speed protocols
Required skills
RTL design, microarchitecture definition, synthesis, timing closure, DFT, GDS delivery, high-speed protocol implementation, cross-functional collaboration
Preferred skills
UVM-based verification, silicon bring-up and debug, Python scripting, small-geometry CMOS design
Technologies
Synopsys, Cadence, UALink, UCI, PCIe Gen 6/7, ESUN, Ethernet, UVM
Responsibilities
Define microarchitecture and implement synthesizable RTL for complex switch ASIC blocks; Drive block-level execution through synthesis, timing closure, gate-level simulation, DFT, and GDS delivery; Partner with verification engineers to define plans, debug failures, and improve coverage; Support silicon bring-up, lab debug, and root-cause analysis for complex connectivity issues; Provide technical leadership, prioritize workstreams, and communicate risks and progress to stakeholders.
