Principal Verification Engineer
Core
Lead full lifecycle functional verification for complex server and networking ASICs and SoCs, ensuring robust design quality through test planning, execution, and coverage closure.
Role type
Principal Design Verification Engineer (SoC/ASIC)
Builds
Cutting-edge SoC designs for server and networking applications
Domain
Semiconductor hardware design, server infrastructure, networking
Required skills
SystemVerilog, UVM, C/C++, Python, directed verification, constrained-random verification, coverage analysis, debugging, test sequence development, emulation platforms, switching architectures
Preferred skills
Verification IP for PCIe/Ethernet/InfiniBand, Network-on-Chip (NoC) architectures, Ethernet/PCIe switching, hardware-software co-verification
Technologies
SystemVerilog, UVM, C/C++, Python, emulation platforms
Responsibilities
Lead functional verification including test planning, development, execution, and coverage analysis; Collaborate with software and system validation teams on emulation platforms; Debug test failures and close functional coverage gaps; Work with RTL designers to troubleshoot design issues; Drive verification strategy and methodology for SoCs; Apply directed and constrained-random verification techniques
Seniority
Principal, hands-on IC
