Senior ASIC Package Design Engineer
Core
Designing advanced ASIC package architecture for high-performance mixed-signal and digital SoCs, focusing on flip-chip BGA and multi-chip module solutions for high-power satellites.
Role type
Senior IC ASIC Package Design Engineer
Builds
High-pin-count, high-speed, power-dense ASIC packages for satellite platforms
Domain
Aerospace / Semiconductor Packaging
Required skills
FC-BGA package design, substrate stack-up definition, power delivery network (PDN) design, signal integrity (SI) and power integrity (PI) analysis, thermal architecture design, OSAT and substrate vendor management, high-speed SerDes interface design, impedance control planning, via strategy definition, escape routing design
Preferred skills
Multi-chip module (MCM) design, heterogeneous integration (chiplets, interposers), high-speed digital or mixed-signal SoC background, aerospace or high-reliability electronics experience
Technologies
SIWave, HFSS, ADS
Responsibilities
Define ASIC package architecture including substrate stack-up, ball-map, and mechanical constraints; Lead package-level trade studies for cost, performance, PI, SI, thermal, and reliability; Establish package design standards and methodologies; Drive detailed design of FC-BGA packages for high-pin-count ASICs; Define substrate stack-ups, via strategies, and reference plane planning; Partner with silicon and RF teams to co-optimize die floorplans; Support package-level SI/PI strategy and decoupling; Lead thermal architecture including lid selection and heat-spreaders; Manage relationships with external packaging vendors and OSATs; Drive material selection and assembly process optimization
Seniority
Senior, hands-on IC
