芯片综合/STA工程师（上海）
Core
Perform logic synthesis, formal verification, and STA signoff for SoC chips; collaborate on clock/reset schemes, low-power strategies, and timing closure.
Role type
IC chip synthesis and static timing analysis engineer
Builds
SoC chips
Domain
Semiconductor / Digital IC Design
Required skills
Logic synthesis, Static Timing Analysis (STA), Formal verification, Scripting (TCL, Perl, Python), EDA tools (DC, PT, Formality, LEC, Tempus), SoC DFT knowledge
Preferred skills
SoC DFT expertise
Technologies
DC, PT, Formality, LEC, Tempus, SDC
Responsibilities
Execute logic synthesis, formal verification, and STA signoff; Collaborate on clock/reset and low-power solutions; Ensure timing closure before tape-out.
Seniority
Mid-level, hands-on IC
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