Sr Staff Engineer, Synthesis and STA
Core
Own RTL-to-Gate conversion, constraint development, and timing closure to deliver high-performance, low-power chips.
Role type
Senior Staff IC backend design engineer (synthesis and STA)
Builds
Optimized gate-level netlists and timing-closed silicon for automotive, industrial, infrastructure, and IoT SoCs/MCUs
Domain
Semiconductor design (Digital IC, Physical Design, EDA)
Required skills
Static Timing Analysis (STA), Logic Synthesis, PPA optimization, Tcl/Python/Perl scripting, EDA tool expertise (Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC), UPF management, Multi-mode Multi-corner (MMMC) analysis, Formal Verification (LEC), Clock tree synthesis, Constraint development (SDC/UPF)
Preferred skills
Mentoring junior engineers
Technologies
Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC, SystemVerilog, SDC, UPF
Responsibilities
Execute hierarchical and physical-aware synthesis flows to translate RTL to gate-level netlists; Perform block-level and full-chip STA across MMMC scenarios; Develop and manage comprehensive timing and power constraints (SDC/UPF); Optimize clock trees and resolve timing bottlenecks; Automate design flows using scripting languages to reduce TAT.
Seniority
Senior Staff, hands-on IC
