Sr Staff Engineer, STA
Core
Own RTL-to-Gate conversion, constraint development, and timing closure to deliver high-performance, low-power chips.
Role type
Senior Staff Backend Design Expert (Static Timing Analysis & Logic Synthesis)
Builds
Optimized gate-level netlists and timing-closed silicon for automotive, industrial, infrastructure, and IoT SoCs/MCUs.
Domain
Semiconductor EDA / Digital Logic Design
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