Principal Engineer. Virtual Prototype Modeling
Core
Developing SystemC/TLM2.0 based virtual prototypes for SoC and Electronics Systems to enable embedded software development, verification, and deployment.
Role type
Principal Engineer, Virtual Prototype Modeling
Builds
Virtual prototypes of SoC, processors, cache controllers, interconnects, peripherals, NPUs, and ISPs
Domain
Semiconductor / Embedded Systems / Hardware Modeling
Required skills
SystemC, TLM2.0, C, C++, Object-oriented programming, SoC architecture, Bus protocols, Microprocessor/Microcontroller architecture, Embedded Linux, Assembly language, Bare metal testing, Virtual prototype tools (ARM Fast Models, Synopsys Virtualizer, Windriver SIMICS)
Preferred skills
IP-XACT, SystemRDL, SystemC-AMS
Responsibilities
Developing SystemC/TLM2.0 models of IP blocks, CPUs, and SoCs; Defining transaction level models for processors and interconnects; Porting OS and developing device drivers; Verifying models at IP and SoC levels; Developing regressable self-checking test suites; Creating system-level flows and methodologies; Supporting firmware and SW teams in using virtual prototypes
Seniority
Senior, hands-on IC
