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Staff Package Design Engineer

Tempe, Arizona, us💼 Full-time🗓 2026-09-30 → 2026-10-02

Core

Design and deliver next-generation, high-performance semiconductor package solutions including power modules, chiplet-based architectures, FCBGA, SiP, WLCSP, and wire-bonded packages for automotive SoCs, industrial IoT, and AI-enabled embedded platforms.

Role type

Staff IC package design engineer

Builds

Advanced semiconductor packages (power modules, FCBGA, SiP, WLCSP, multi-die/chiplet) for automotive, industrial, and IoT applications

Domain

Semiconductor manufacturing / Advanced packaging

Required skills

Package CAD layout execution, substrate design, bump map creation, escape routing, stack-up structure design, DFM/DFA principles, manufacturing release standards, cross-domain co-design, design rule compliance (DRC/LVS), Engineering Change Order management

Preferred skills

Power module packaging expertise, chiplet-based architecture experience, Tier-1 OSAT interfacing, high-speed routing and impedance control

Technologies

Cadence Allegro Package Designer / SiP Layout, Siemens Xpedition Substrate Integrator

Responsibilities

Execute package layout design for advanced technologies; develop and maintain package CAD databases; manage the full package design cycle from schematic to manufacturing release; create and modify substrate/RDL layouts and bump maps; collaborate with SI/PI, thermal, and silicon teams on co-optimization; ensure compliance with foundry and OSAT design rules

Seniority

Staff, hands-on IC

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