SoC Digital Design Engineer, Multimedia Lab
Core
Design hardware accelerators for advanced video encoding and processing within scalable video codec solutions.
Role type
SoC Digital Design Engineer (Front-end)
Builds
Video codec hardware solutions (FPGA and ASIC) for billions of users
Domain
Semiconductor / Video Processing / SoC Design
Deliverable
production ML models
Required skills
Verilog/SystemVerilog, Digital Circuit Design, Front-end EDA Tools (Spyglass, Design Compiler, PrimeTime), Scripting (Python/Perl/Tcl/Makefile), PPA Evaluation, Clock Domain Crossing, Reset Domain Crossing, Low Power Design (Clock Gating, Power Gating, UPF)
Preferred skills
NPU Architecture, HW/SW Co-design, AI Hardware Acceleration, SoC Performance Profiling, Complex SoC Core Subsystem Integration, Advanced Process Node Tape-out (7nm/5nm/3nm)
Responsibilities
Define SoC architecture and conduct PPA evaluation; Write and maintain RTL code; Perform Lint, CDC, and RDC checks; Collaborate with verification and backend teams for synthesis, STA, and power optimization; Formulate and apply low-power design strategies.
Seniority
Mid-level, hands-on IC
