ASIC设计工程师（Scale up内存语义方向） - 芯片研发
Core
Design and develop ASIC microarchitecture and RTL for data center network chips, focusing on scale-up memory semantics and RDMA protocol optimization.
Role type
Senior IC ASIC Design Engineer (Network/Scale-up Memory Semantics)
Builds
Custom hardware accelerators and network chips for data center infrastructure
Domain
Semiconductor / Data Center Networking
Deliverable
production ML models | product features
Required skills
ASIC microarchitecture design, RTL development (Verilog), RDMA protocol implementation, scale-up memory semantics (load/store/atomic), computer architecture, bus interface protocols (MAC, PCIe, AMBA), memory technologies (DDR, HBM), scripting (TCL, Perl, Python)
Preferred skills
RDMA pre-research and paper publication, network chip tape-out experience, AI training parallelism strategies, high-speed network operations, RDMA kernel/user-space drivers
Responsibilities
Analyze data center ASIC requirements and design microarchitecture, research and simulate high-speed interconnect trends, perform software-hardware co-optimization and chip modeling for performance analysis
