Staff Verification Engineer - Security IP
Core
Design Verification Engineer specializing in Security IP for SoC designs, focusing on Cryptography, Key Management, and Hardware Root of Trust.
Role type
Staff Verification Engineer (Security IP)
Builds
Security IP and subsystems for pioneering SoC designs
Domain
Semiconductor / Hardware Security
Required skills
SystemVerilog UVM, Verilog HDL, C, Perl, Python, Tcl, Formal verification, Hardware/Firmware co-verification, Multi-clock domain design, AXI/AHB protocols, Low-level programming (Assembler), Firmware debug
Preferred skills
ARM System Architectures, Clock domain crossing verification, Power aware verification
Technologies
UVM, SystemVerilog, Verilog, C, Perl, Python, Tcl, ARM
Responsibilities
Develop test plans, testbenches, and verification models; Debug test failures and issues; Partner with design team for functional sign-off and coverage; Mentor team members; Contribute to verification methodologies
Seniority
Staff, hands-on IC with mentorship