Functional Verification Engineer
Core
Develop and execute testbenches to verify the functional correctness of DDR4/DDR5 digital designs at the block and system level.
Role type
Senior IC hardware verification engineer (DDR protocol)
Builds
DDR PHY and memory controller IP verification plans, testbenches, and compliance reports
Domain
Semiconductor hardware verification, DDR memory protocols
Required skills
UVM, SystemVerilog, DDR4/DDR5 protocol specifications, signal integrity analysis, post-silicon bring-up, JEDEC compliance testing, regression automation, root cause analysis
Preferred skills
LPDDR4/5 experience, formal verification, Python/TCL scripting, SPICE simulation
Technologies
Synopsys VCS, Cadence Xcelium, Verdi, DVE, SimVision, Teledyne LeCroy protocol analysers, Git, Perforce
Responsibilities
Develop DDR4/DDR5 verification plans covering functional, performance, and compliance testing; Build and maintain UVM-based testbenches for DDR PHY and memory controller IP verification; Lead post-silicon DDR bring-up, characterisation, and margin analysis activities; Perform signal integrity analysis and correlate simulation results with lab measurements; Drive JEDEC DDR4/DDR5 compliance testing and liaise with memory vendors; Debug and root-cause DDR failures across simulation, emulation, and silicon environments
Seniority
Senior, hands-on IC
