Formal Verification Engineer
Core
Apply formal methods to exhaustively verify interconnect fabric, protocol bridges, and link-layer logic for silicon chips.
Role type
Senior IC formal verification engineer (silicon)
Builds
Verified interconnect fabrics, protocol bridges, and link-layer logic
Domain
Semiconductor hardware design and verification
Deliverable
production ML models | product features
Required skills
formal verification, model checking, equivalence checking, System Verilog, Verilog, abstraction modeling, BDD, DFG
Preferred skills
cross-functional collaboration, technical documentation, innovation in verification tools
Technologies
formal verification tools, BDD solvers, DFG analyzers
Responsibilities
Develop and execute formal verification test and coverage plans; Create abstraction models to enable convergence; Generate and validate formal proofs; Collaborate with architecture and RTL design teams; Maintain formal verification infrastructure; Document test plans and drive technical reviews
Seniority
Senior, hands-on IC
