Senior Package Design Engineer
Core
Lead co-design activities bridging silicon design, package architecture, and product development for advanced DRAM and memory products targeting Mobile, Automotive, AI, Edge/Cloud, and Data Center applications.
Role type
Senior IC package design engineer (memory/semiconductor)
Builds
High-performance, reliable, and manufacturable package designs for DRAM and NAND memory products
Domain
Semiconductor industry, advanced memory packaging (DRAM, NAND)
Required skills
Advanced memory substrate design, EDA tools (Cadence Allegro, Siemens Xpedition), flip chip and wire bond interconnects, BEOL/RDL flows, Signal Integrity (SI) and Power Integrity (PI) analysis, OSAT/assembly partner collaboration, DFM reviews, package layout (floorplanning, placement, routing)
Preferred skills
Advanced DRAM packaging (LPDDR, HBM, GDDR), TSV-based stacking, micro-bump layout, Chip Package Interaction (CPI) analysis, co-design engagement leadership, Assembly DOE definition, DFMEA reviews, mechanical drawing tools (AutoCAD), 2.5D/3D-IC, FOWLP, System-in-Package (SiP)
Technologies
Cadence Allegro Package Designer+, Cadence Integrity 3D-IC Platform, Siemens Xpedition, AutoCAD
Responsibilities
Lead co-design activities to define new product concepts and optimize die floorplans and interconnection schemes; Define and optimize package architectures including substrate stack-up and interconnect schemes; Lead package layout activities including floorplanning, placement, and high-density routing; Partner with SI and PI teams to incorporate simulation analysis into design optimization; Collaborate with assembly engineering and OSAT partners to manage DFMEA reviews and ensure HVM specifications; Support continuous improvement initiatives including design rule system development and competitive analysis
Seniority
Senior, hands-on IC
