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Sr Design Readiness Engineer

Boise, ID - Main Site💼 Full-time🗓 2026-09-01 → 2026-09-29

Core

Lead pre-silicon readiness activities for new DRAM products, bridging design intent, validation execution, and silicon learning to ensure product quality and manufacturing readiness.

Role type

Senior IC Design Readiness Engineer (Semiconductor/DRAM)

Builds

New DRAM memory products and storage solutions

Domain

Semiconductor industry, DRAM technology, silicon validation, and product engineering

Required skills

semiconductor device behavior analysis, circuit analysis, validation methodology, signal integrity, test development, reliability engineering, root-cause analysis, experiment planning, risk assessment, cross-functional leadership, technical mentoring

Preferred skills

PhD or MS in EE/CS/Semiconductor, experience with AI-enabled engineering tools, leading technical workstreams, shaping cross-functional engineering practices

Technologies

AI tools for technical research, data synthesis, debug planning, experiment tracking, documentation, and workflow automation

Responsibilities

Lead pre-silicon readiness activities including risk assessment, DFMEA preparation, and validation planning; Partner with Design, Verification, and Product Engineering teams to identify risks and align debug priorities; Analyze circuit behavior, silicon data, and failure signatures to drive structured investigations; Influence product readiness decisions by connecting design intent with manufacturing constraints; Mentor engineers and strengthen technical practices across DRAM programs; Apply AI-enabled ways of working to improve engineering productivity and streamline workflows

Seniority

Senior, hands-on IC with technical leadership

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