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Sr Design Readiness Engineer

Boise, ID - Main Site💼 Full-time🗓 2026-09-02 → 2026-09-29

Core

Lead design readiness activities for new DRAM products, including risk assessments, validation planning, and root-cause investigations of silicon findings.

Role type

Senior IC design readiness engineer (DRAM)

Builds

New DRAM memory products

Domain

Semiconductor industry, DRAM technology, silicon validation

Required skills

DRAM design, silicon validation, device characterization, circuit debug, reliability engineering, test development, root-cause analysis, statistical analysis, cross-functional leadership

Preferred skills

PhD or MS in engineering/science, mentoring engineers, silicon debug, production test coverage, margin characterization, AI proficiency, Agentic AI tools

Technologies

AI-enabled tools, Agentic AI tools

Responsibilities

Lead design readiness activities for new DRAM products, Partner with cross-functional teams to identify product risks and prioritize debug activities, Drive root-cause investigations of silicon findings, Influence product readiness decisions, Mentor engineers and improve technical practices

Seniority

Senior, hands-on IC

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