Process Integration Engineer, APTD
Core
Develop and integrate semiconductor process flows for next-generation memory and packaging technologies, focusing on Wafer-Level Technology and reconstructed substrates.
Role type
Senior IC process integration engineer (semiconductor)
Builds
Next-generation memory products (HBM) and advanced packaging solutions
Domain
Semiconductor manufacturing, memory technologies, advanced packaging
Deliverable
production ML models
Required skills
Semiconductor process integration, experiment design and execution, statistical analysis, Design of Experiments (DoE), root-cause analysis, cross-functional collaboration, AI tools for engineering workflows
Preferred skills
Advanced packaging technologies (wafer-level, fan-out, 2.5D/3D integration, TSV, microbump, hybrid bonding, chiplet), Wafer-Level Technology flows, process transfer to high-volume manufacturing, device/package reliability testing, machine learning for yield improvement
Technologies
AI tools, statistical analysis software, DoE frameworks
Responsibilities
Lead technical integration projects for new memory and advanced packaging technologies; Design and complete experiments to assess process performance, variability, reliability, and yield; Solve complex integration issues using data from inline, defect, parametric, probe, reliability, and package-level testing; Partner across engineering fields to develop and qualify new technologies; Apply AI tools to data analysis, experiment planning, documentation, and technical problem-solving
