Design Verification Engineer
Core
Develop and implement verification plans, test scenarios, and automation solutions for next-generation DRAM and emerging memory technologies.
Role type
Design Verification Engineer
Builds
High-density memory products with advanced functionality and ultra-high-speed interfaces
Domain
Semiconductor / Memory / DRAM
Required skills
SystemVerilog, UVM, SystemVerilog Assertions (SVA), simulation tools (SpectreFX, Xcelium), Python/Perl scripting, debugging, root-cause analysis
Preferred skills
DRAM/memory product experience, Cadence/Synopsys tools, AI-assisted engineering tools
Technologies
SystemVerilog, UVM, SpectreFX, Xcelium, Python, Perl, Cadence, Synopsys
Responsibilities
Develop verification environments and automation solutions; Analyze functionality and timing requirements to support coverage; Debug design and verification issues; Support bug tracking and verification signoff; Partner with design engineers to resolve technical challenges; Contribute to verification strategies for new product features
Seniority
Mid-level, hands-on IC
