Senior DFT Engineer
Core
Design-for-Test (DFT) architecture, verification, and post-silicon validation for complex semiconductor chips.
Role type
Senior IC DFT Engineer
Builds
Test access mechanisms, IO BIST, memory BIST, and scan compression for next-generation GPU products.
Domain
Semiconductor / Hardware Design
Required skills
DFT architecture, scan test planning, BIST (memory/IO), fault modeling, ATPG, fault simulation, silicon debug, ATE bring-up, Perl/Python/Tcl scripting
Preferred skills
RTL design, clock design, STA, place-and-route, power analysis
Technologies
ATE, vendor verification tools
Responsibilities
Implement state-of-the-art DFT designs, develop and deploy DFT methodologies, mentor junior engineers on test designs and trade-offs
Seniority
Senior, hands-on IC
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