SOC DFT Engineer
Core
Define SOC chip-level and sub-system level DFT architecture, manage scan insertion and timing constraints, and support post-silicon diagnosis and manufacturing process (MP) issues.
Role type
SOC DFT Engineer
Builds
SOC chips and sub-systems
Domain
Semiconductor / Digital Integrated Circuits
Required skills
DFT architecture definition, scan insertion, ATPG pattern generation and simulation, ATPG post-silicon diagnosis, Equivalence check, Scan SDC constraint, Timing sign-off, Power analysis, Timing ECO
Preferred skills
MP support, DRC check, coverage improvement, pattern count reduction
Technologies
ATPG, SDC, Equivalence Check tools
Responsibilities
Define DFT architecture and scan constraints, support physical implementation for DFT parts, assist in resolving manufacturing process issues
Seniority
Individual Contributor
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