Physical Design Methodology Lead
Core
Lead backend design automation for advanced process node SoC and ASIC implementation, enabling robust RTL-to-GDS flows.
Role type
Senior IC physical design methodology engineer
Builds
Production-ready RTL-to-GDS flows for complex SoC and IP programs
Domain
Semiconductor physical design and design automation
Required skills
RTL-to-GDS flow expertise, timing signoff and STA, power grid and IR/EM analysis, Tcl/Python/Perl scripting, EDA tool ecosystem knowledge, cross-functional technical leadership, automation framework development, congestion analysis, ECO implementation, physical verification
Preferred skills
Machine learning optimization, agentic/AI-assisted design automation, competitive benchmarking, vendor roadmap influence
Technologies
Synopsys, Cadence, Siemens EDA, Tcl, Python, Perl, shell scripting, SDC, UPF, STA, CTS, P&R
Responsibilities
Own and improve backend RTL-to-GDS implementation flows for quality, scalability, and runtime; Drive methodology development across place and route, CTS, timing closure, and power integrity; Partner with design, DFT, verification, and foundry teams to meet tapeout requirements; Lead initiatives from concept through deployment and production support; Establish repeatable best practices, reference flows, and automation frameworks; Work with EDA vendors to adopt latest technologies in physical implementation and AI-assisted automation; Debug complex flow, tool, and timing issues; Promote automation-first thinking via scripting and regression systems; Provide deployment support and hands-on technical leadership.
Seniority
Senior, hands-on IC
