Staff Engineer, Physical Design
Core
Drive end-to-end physical design implementation (Synthesis, Floorplanning, P&R, Signoff) for next-generation IPs, translating complex RTL into high-performance silicon while optimizing Power, Performance, and Area (PPA).
Role type
Staff Physical Design Engineer
Builds
Next-generation RISC-V IP blocks including CPUs, high-speed interconnects, cache/memory hierarchies, and specialized accelerators
Domain
Semiconductor chip design / RISC-V architecture
Required skills
End-to-end physical design flow expertise, RTL-to-physical co-optimization, advanced PPA optimization techniques, complex timing and congestion debugging, EDA tool mastery (Synopsys/Cadence), cross-functional collaboration
Preferred skills
Experience with 7nm and below process nodes, deep familiarity with specific IP domains (CPUs, fabrics, memory), mentorship of junior engineers
Technologies
Synopsys Fusion Compiler, Synopsys PrimeTime, Cadence Innovus, Cadence Tempus
Responsibilities
Drive complete physical design flow for major sub-systems and IP blocks; Partner with RTL/Architecture teams to identify and resolve physical bottlenecks; Apply advanced techniques for power efficiency, reliability, and bandwidth maximization; Act as subject matter expert for complex implementation challenges; Mentor junior engineers and champion best practices
Seniority
Staff, technical leadership & hands-on IC