Digital Verification Engineer (New Grad)
Core
Verify digital and mixed-signal ICs (power management, signal management, mixed signal functions) using industry standard ASIC tools.
Role type
Digital Verification Engineer (New Grad)
Builds
Digital verification environments, test cases, assertions, and verification IPs for power management and mixed-signal products.
Domain
Semiconductor / Integrated Power Semiconductors
Required skills
SystemVerilog, UVM, behavioral/RTL coding, ASIC development process, digital design techniques, test plan generation, code/functional coverage analysis, gate-level verification, scripting/automation
Preferred skills
Embedded designs/firmware development, power management industry knowledge, I2C/I3C/SPI/USB/PMBUS protocols, TCL/Python/C++
Technologies
Digital Simulators, synthesis tools, DFT, LEC, STA
Responsibilities
Generate test plans based on design requirements and datasheets; Create Digital Verification environments with UVM and SystemVerilog; Write Digital and mixed-Signal testcases and assertions/checkers; Analyze and debug test results, code coverage and functional coverage; Develop Verification IPs and standard tests, environments, checkers; Perform automation and scripting; Conduct Gate-Level verification.
Seniority
Entry-level, New Grad
