CPU Design Engineer
Core
Architecting and implementing high-performance, area-efficient Soft CPU cores optimized for Altera FPGA architectures.
Role type
Senior IC CPU Design Engineer (FPGA)
Builds
Soft CPU cores (RISC-V Nios V ecosystem) for programmable logic
Domain
Semiconductor / FPGA / Processor Architecture
Required skills
CPU micro-architecture, RTL design (SystemVerilog/Verilog), FPGA synthesis, timing closure, PPA optimization, processor pipeline design, memory hierarchy design
Preferred skills
RISC-V ISA specification, custom instruction insertion, AMBA AXI/Avalon interfaces, compiler toolchains (GCC/LLVM), Python/Tcl/Shell scripting
Technologies
Altera Quartus Prime Pro, Platform Designer (Qsys), TimeQuest Timing Analyzer, Signal Tap, RISC-V, SystemVerilog, Verilog
Responsibilities
Micro-architect and implement Soft CPU cores for Altera FPGA; Optimize processor pipelines for PPA using ALMs, memory blocks, and DSP slices; Drive design through synthesis and timing closure; Implement configurable features like instruction set extensions; Collaborate on verification and hardware validation
Seniority
Senior, hands-on IC
