Senior Manager, Design Verification Engineering
Core
Lead end-to-end pre-silicon design verification for complex digital SoCs, microprocessor-based designs, and AI/ML accelerators.
Role type
Senior Manager, Design Verification Engineering
Builds
Highly integrated SoC and subsystem solutions for the Intelligent Edge
Domain
Semiconductor / Digital SoC Design Verification
Deliverable
production ML models
Required skills
UVM-based testbench development, SystemVerilog/Verilog, formal verification, constrained-random verification, NoC/interconnect verification, power-aware verification (UPF), protocol verification (AXI/AHB, I2C, SPI, Ethernet), test planning, coverage analysis, C/C++, Python/TCL scripting
Preferred skills
Mixed-signal/analog verification (ADC/DAC/PLL/PHY), processor-based systems (ARM, RISC-V, Tensilica), AI/ML accelerator verification
Technologies
UVM, SystemVerilog, Verilog, Python, TCL, Shell, C, C++, SystemC, AXI, AHB, DMA, SVI3, I2C, SPI, Ethernet, UART, NoC, UPF, GLS
Responsibilities
Lead end-to-end SoC verification from planning to signoff; Define and drive verification strategies, architecture, and methodologies; Mentor team members and provide technical leadership; Collaborate with architecture and design teams to align on requirements; Drive pre-silicon readiness with emulation, FPGA, and software teams; Architect scalable testbench environments and DV flows; Perform system-level performance verification and analysis.
Seniority
Senior Manager, hands-on IC leadership
