Principal Design Engineer
Core
Lead design verification for complex electronic designs, specifically focusing on memory IP verification.
Role type
Principal Design Verification Engineer
Builds
Verified memory IP (DDR/HBM/GDDR) and complex digital designs
Domain
Semiconductor / VLSI / Memory IP
Required skills
System Verilog, UVM, functional verification fundamentals, environment planning, test plan generation, project leadership
Preferred skills
Memory IP verification (DDR/HBM/GDDR)
Technologies
System Verilog, UVM
Responsibilities
Develop functional verification environments, generate test plans, lead verification projects from concept to closure, verify complex designs
Seniority
Senior, hands-on IC
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