Lead Design Engineer - Verification
Core
Lead verification engineer for high-performance Consumer PHYs (eUSB2v2, USB4, PCIe, eDP/DP, SATA) using UVM methodologies.
Role type
Senior IC verification engineer (high-speed serial interfaces)
Builds
Verification environments, testbenches, and signoff quality metrics for physical interface IPs
Domain
Semiconductor / High-speed serial protocols (USB, PCIe, DP, SATA)
Required skills
SystemVerilog, UVM, constrained-random verification, functional coverage, assertions (SVA), regression management, root cause analysis, low-power verification, clock/reset domain crossing checks, gate-level simulation, formal techniques, VIP integration, firmware/hardware interaction verification
Preferred skills
High-speed serial link IP verification (PHY/PCS/controller), Cadence tool suite (Xcelium, vManager, Verisium, JasperGold, Palladium), UPF/CPF, mixed-signal co-simulation, Python/Perl/Tcl scripting, AI-assisted verification, controller+PHY subsystem-level verification
Responsibilities
Develop and maintain UVM-based verification environments from block to PHY top level; create verification plans and coverage models from protocol specs; run regressions and debug RTL/testbench issues; apply low-power and formal verification techniques; integrate commercial VIPs and verify firmware/hardware flows; support pre/post-silicon debug and collaborate on verification infrastructure
Seniority
Senior, hands-on IC
