Senior Static Timing Analysis (STA) Methodology Engineer
Core
Architect and maintain production Static Timing Analysis (STA) flows to drive signoff closure for high-performance, low-power SoC designs targeting 5G, IoT, and LEO satellite applications.
Role type
Senior IC Static Timing Analysis (STA) Methodology Engineer
Builds
Production STA flows, CAD utilities, and timing closure strategies for advanced technology nodes
Domain
Semiconductor design, SoC, 5G, IoT, LEO satellite communications
Required skills
Static Timing Analysis (STA) methodology, PrimeTime (PT-SI, PTPX, PT-ECO), Tcl/Python/Perl scripting, timing constraint debugging, clock tree synthesis (CTS), MMMC analysis, timing ECO flows, noise/crosstalk/OCV analysis
Preferred skills
Advanced process nodes (7nm/5nm), low-power design (DVFS, power gating), interface protocol timing (DDR, PCIe, USB, SerDes), ML-assisted EDA optimization
Technologies
PrimeTime, Tcl, Python, Perl, CTS, MMMC
Responsibilities
Lead cross-functional efforts to solve complex timing challenges across multiple IPs and technology nodes; Develop and enhance STA methodologies across the full RTL-to-GDS flow; Architect, optimize, and maintain production STA flows using industry-standard EDA tools; Drive signoff correlation and closure using PrimeTime and related tools; Debug timing constraints and resolve timing correlation issues; Explore and deploy data-driven and ML-assisted techniques to improve STA automation; Design, implement, and maintain scalable CAD utilities and STA flow components; Provide timing closure guidance and mentorship to design and physical design engineers
Seniority
Senior, hands-on IC
