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Principal Physical Design Engineer

United States, California, Mountain View💼 Full-time🗓 2026-07-14 → 2026-09-29

Core

Lead and execute Physical Design activities at block, sub-chip, and full-chip levels, driving implementation phases from floorplanning to signoff.

Role type

Principal Physical Design Engineer

Builds

Complex ASICs in leading edge technology

Domain

Semiconductor / VLSI Design

Required skills

Floorplanning, Synthesis, Placement and optimization, Clock Tree Synthesis (CTS), Routing, Static Timing Analysis (STA), Physical Verification, Formal Equivalency, Power optimization, IR-drop analysis, Electromigration (EM) analysis, Technology node evaluation, IP selection, EDA tool selection

Preferred skills

Leading team to deliver planned PD goals, Methodology improvements, Automation development

Technologies

EDA tools, Custom clocking, Tapeout

Responsibilities

Lead and execute Physical Design activities at block, sub-chip, and full-chip levels; Contribute to Physical Design flow development, automation, and methodology improvements; Evaluate and recommend technology nodes, IP selection, EDA tools, and vendor solutions; Provide status updates on progress, risks, and mitigation plans; Drive all phases of implementation including Floorplanning, Synthesis, Placement, CTS, Routing, STA, Verification, and Power optimization.

Seniority

Principal, hands-on IC with leadership

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