ASIC Design Engineer
Core
Design and manufacture high-performance, power-efficient processor and system-on-chip (SoC) for Apple products and services.
Role type
Senior IC ASIC Design Engineer (IP design)
Builds
High-bandwidth processing pipelines and functional SoC designs for consumer devices
Domain
Consumer electronics / Semiconductor / Digital Logic
Deliverable
production ML models | product features
Required skills
RTL design (Verilog/System Verilog), micro-architectural specification, digital design, collaboration with architecture/verification teams, low-power design techniques, on-chip bus protocols (AMBA), front-end implementation (synthesis, timing, area/power analysis), scripting (Python/Perl/TCL)
Preferred skills
USB4/USB3/PCIe/DisplayPort experience, AI/ML applications knowledge, synthesis and timing closure expertise
Technologies
Verilog, System Verilog, Python, Perl, TCL, AMBA (AXI, AHB, APB)
Responsibilities
Write high-quality RTL with embedded assertions and cover points; Write detailed micro-architectural specifications; Collaborate with multi-functional teams to optimize performance, power, and area; Debug and verify functionality and performance with verification teams
Seniority
Senior, hands-on IC
