PHY RTL Design Engineer
Core
Design and development of signal processing intensive SoCs for wireless communication, focusing on PHY layer algorithms and system design integration.
Role type
Senior IC RTL design engineer (wireless PHY)
Builds
ASICs for wireless connectivity in Apple products
Domain
Consumer electronics, wireless communications
Deliverable
production ML models
Required skills
PHY/RTL development, signal processing algorithms, MATLAB/C modeling, low latency architecture, DV coverage derivation, synthesis and timing constraints, pre-silicon validation, RF lab optimization
Preferred skills
Low power SoC development, Bluetooth protocol, WLAN IEEE 802.11 protocol
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