SoC Physical Design Engineer, PnR
Core
Physical implementation of design partitions from netlist to tapeout for highly complex System on Chip (SoC) utilizing innovative process technology.
Role type
Senior IC SoC Physical Design Engineer (PnR)
Builds
SoC chips for Apple hardware products
Domain
Semiconductor / SoC Physical Design
Required skills
partition-level P&R implementation, floorplanning, clock and power distribution, timing closure, physical and electrical verification, physical design flow methodology, industry standard EDA tools
Preferred skills
large SoC design experience (>20M gates), high-frequency design (>1GHz), sub-10nm technology node experience
Responsibilities
Collaborate with logic design teams on partition architecture and early physical aspects, complete netlist to GDS2 implementation meeting schedule and design goals, perform timing/physical/electrical verification and drive signoff closure, resolve and improve physical design and flow issues
Seniority
Senior, hands-on IC