ASIC Design Engineer — Pixel IP
Core
Design high-performance, low-power pixel processing engines for capturing, improving, compressing, and displaying digital still images and video.
Role type
Front-end ASIC Design Engineer (Pixel IP)
Builds
Digital signal processing pipelines for camera and video subsystems
Domain
Consumer electronics / Semiconductor / Image processing
Deliverable
production ML models | product features
Required skills
RTL design (Verilog/System Verilog), micro-architectural specification, digital hardware design, synthesis, timing/area/power optimization, cross-functional collaboration
Preferred skills
AMBA protocols (AXI, AHB, APB), scripting (Python, Perl, TCL), High-Level Synthesis, SystemC/C++, digital signal processing concepts
Technologies
Verilog, System Verilog, Python, Perl, TCL, SystemC, C++, AMBA (AXI, AHB, APB)
Responsibilities
Write high-quality RTL with embedded assertions and cover points; Write detailed micro-architectural specifications; Collaborate with cross-functional teams to optimize performance, power, and area; Synthesize designs and optimize for power, timing, and area; Debug and verify functionality and performance with verification teams
Seniority
Mid-level, hands-on IC
