Lead Engineer – IC Design (STA Lead )
Core
Lead Physical Design Engineer responsible for end-to-end backend implementation flow, timing sign-off, and PPA optimization for high-performance SoCs and ASICs.
Role type
Senior IC physical design engineer (STA Lead)
Builds
High-performance System-on-Chips (SoCs) and Application-Specific Integrated Circuits (ASICs)
Domain
Semiconductor / VLSI / ASIC Physical Design
Required skills
Static Timing Analysis (STA), Synthesis, Place & Route, Low Power Design (UPF), Physical Verification, EDA Tool Automation, Timing Closure, PPA Optimization
Preferred skills
Hierarchical Design Methodologies, DFT, Floor Planning, Multi-clock/Multi-voltage Designs, Team Leadership (4-10 members), Scripting (Perl/Tcl/Python)
Technologies
Cadence (Genus, Innovus, Tempus, LEC, CLP), Synopsys (ICC2, Fusion Compiler, PrimeTime)
Responsibilities
Manage timing constraints and execute STA for digital blocks and top-level designs; Lead end-to-end physical design flow from RTL handoff to GDSII; Optimize PPA metrics and resolve critical path issues via timing ECOs; Collaborate with front-end RTL, DFT, and verification teams; Mentor junior engineers on design excellence and methodology.
Seniority
Senior, hands-on IC