IC前端工程师/IP设计工程师-Data（深圳）
Core
IC Front-end Engineer responsible for IP module detailed design, SOC integration, RTL design, and timing verification.
Role type
IC Front-end Engineer (Digital)
Builds
Digital IC chips and IP modules
Domain
Semiconductor / Digital Integrated Circuits
Required skills
RTL design (Verilog/SystemVerilog), EDA tools (Synopsys/Cadence/Mentor), Digital IC design flow, Power/Area/Performance analysis, Post-layout simulation, Linux/Unix, Scripting (Tcl/Perl/Python)
Preferred skills
SOC chip experience, DV/SV/UVM verification methodology
Technologies
Verilog, SystemVerilog, Synopsys, Cadence, Mentor, Linux, Tcl, Perl, Python
Responsibilities
Perform IP module detailed design and SOC integration based on chip requirements; Define hardware/software partitioning and complete RTL design; Conduct timing checks and assist with FPGA/EMU verification; Analyze power, area, and performance at module level; Support back-end design and perform post-layout simulation; Participate in chip testing and debugging.
