Senior SoC Physical Layout & Full-Chip Integration Engineer
Core
Lead full-chip floorplanning, physical integration, and tapeout for advanced-node silicon development vehicles.
Role type
Senior IC physical design engineer (full-chip integration)
Builds
Custom layout methodologies and full-chip silicon platforms for advanced process nodes
Domain
Semiconductor manufacturing / Advanced-node physical design
Required skills
Custom/analog/mixed-signal layout design, Front-end (FEOL) layout design rules, Physical verification (LVS, DRC, DFM), Tcl/Python/SKILL scripting, Floorplanning, RDL/bump planning, PowerVia implementation
Preferred skills
PDK collaboration, Tapeout schedule management, Custom layout environments (Cadence Virtuoso), NDM flows
Technologies
Calibre, ICV, Cadence Virtuoso, Tcl, Python, SKILL
Responsibilities
Lead full-chip floorplanning and physical integration, Develop custom layout methodologies, Drive physical verification closure, Analyze advanced-node design rules, Develop automation solutions, Coordinate cross-functional tapeout activities
Seniority
Senior, hands-on IC