MTS, DEG Design Verification
Core
Leading design and verification strategy for advanced DRAM products, focusing on silicon debugging, coverage closure, and methodology innovation.
Role type
Senior IC design verification engineer (DRAM)
Builds
Next-generation DRAM memory solutions
Domain
Semiconductor / Memory / DRAM
Required skills
DRAM verification, circuit analysis at transistor level, silicon debugging, HSPICE, Finesim, Verilog, SystemVerilog, CMOS fundamentals, verification planning, coverage closure
Preferred skills
UVM, mixed-signal verification, DDR5+ architectures, verification methodology development, mentoring, Python programming, AI-assisted EDA automation
Technologies
HSPICE, Finesim, Verilog, SystemVerilog, Python, UVM, ClaudeCode
Responsibilities
Lead DRAM verification innovation and technical strategy; Collaborate globally to define best-known verification methods; Drive verification planning, coverage closure, and silicon debugging; Evaluate and implement new tools and flows; Mentor engineers and provide expert guidance to senior leadership
Seniority
Senior, hands-on IC with mentorship responsibilities
