STA Engineer
Core
Execute Static Timing Analysis (STA) for high-speed communication devices, managing constraints, models, and timing ECOs from RTL to sign-off.
Role type
STA Physical Design Engineer
Builds
High-speed communication chips with high throughput and low latency
Domain
Semiconductor Physical Design / Networking
Required skills
STA execution, RTL constraint definition, DFT constraint quality assurance, timing ECO generation, flow development
Preferred skills
Physical design flows (PNR, STA, physical verification), DFT flows (ATPG, Mbist, Ijtag), DFT timing closures, CDC analysis, EDA tools (Synopsys, Cadence)
Responsibilities
Generate timing ECOs for block and full chip levels, develop design flows, ensure DFT constraint quality, work on pre and post silicon aspects
Seniority
Mid-level, hands-on IC
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