Senior Principal Physical Design Engineer
Core
Lead and execute advanced physical design activities for complex SoC and IP blocks, achieving performance, power, and area targets.
Role type
Senior Principal IC physical design engineer
Builds
Large-scale digital designs from RTL to GDSII for cutting-edge semiconductor products
Domain
Semiconductor / ASIC Physical Design
Required skills
RTL-to-GDSII physical design, floor planning, power planning, place and route, clock tree synthesis, static timing analysis (STA), formal verification, DRC, LVS, low-power design techniques (clock gating, power gating, multi-voltage), EDA tool optimization, scripting automation (Tcl, Perl, Python), semiconductor physics, DFM principles
Preferred skills
Mentorship of junior engineers, evaluation of new EDA tools, defining design specifications from physical implementation perspective
Technologies
Cadence Innovus/Tempus, Synopsys Fusion Compiler/PrimeTime, Ansys RedHawk/PathFinder
Responsibilities
Lead physical design execution from RTL to GDSII, optimize design flows and scripts, perform critical path analysis, collaborate with design/architecture/verification teams, mentor engineers, integrate new EDA tools, develop low-power techniques, generate design documentation
Seniority
Senior, hands-on IC with mentorship responsibilities