Senior Physical Design Engineer
Core
Deliver high-quality physical implementation of complex SoC/IP blocks from netlist to GDSII, ensuring timing, power, area, and reliability targets are met.
Role type
Senior IC physical design engineer
Builds
Complex digital blocks and subsystems for SoC chips
Domain
Semiconductor / VLSI / Digital IC Design
Required skills
Floorplanning, Power Planning, Placement Optimization, Clock Tree Synthesis (CTS), Routing, Timing Closure, Physical Verification, Static Timing Analysis (STA), Multi-Mode Multi-Corner (MMMC) methodologies, Crosstalk/SI Analysis, ECO Flows, Timing Signoff, IR Drop Analysis, Electromigration (EM) Analysis, DRC/LVS Closure, Reliability Checks
Preferred skills
Advanced node design implementation, Automation flows development
Technologies
Cadence Innovus, Synopsys ICC2, PrimeTime, Tempus, RedHawk, Voltus, StarRC, Quantus, Calibre
Responsibilities
Own end-to-end physical design implementation of complex digital blocks/subsystems, Drive floorplanning, power planning, placement, CTS, routing, timing closure, and physical verification, Perform design optimization for PPA (Power, Performance, Area) targets, Execute timing closure across multiple operating modes and process corners, Analyze and resolve setup, hold, SI, IR-drop, EM, and congestion issues, Develop and enhance PD methodologies, automation flows, and scripts to improve productivity
Seniority
Senior, hands-on IC